Low Effort, High Accuracy Network-on-Chip Power Macro Modeling

This paper deals with a new and effective methodology to minimize the Design of Experiments (DoE) needed to characterize a set of energy macro models of innovative Network-on-Chip architectures. By properly combining regression (i.e. polynomial) and interpolation (i.e. table-based) techniques, this methodology aims to reduce the overwhelming complexity of sampling the huge, non-linear design space involved with the system operations of a highend parametric on-chip-network module. Eventually, the outcoming power models are linked to a standard SystemC simulator by means of a specific class library extension, running at Bus Cycle Accurate (BCA) and Transaction Modeling Level (TLM). In this context, the power model is accurate and highly correlated, with an average error of 2% and a RMS of 0.015 mW vs. the reference power figures, measured on the gate level mapped design. Without affecting the general applicability of our approach, the proposed methodology is exploited through an automatic model characterization and building flow, targeting an industrial on-chip communication IP (STBus).The experimental figures show that our DoE optimization techniques are able to trade-off power accuracy with model building cost, leading up to 90% reduction of the sampling space.